As is well known in the art, polyphase DC motors are commonly used in hard disk drives in modern personal computers and workstations, as well as in other important industrial and consumer applications. Particularly in the case of disk drive motors, control of the speed of the motor is important in providing high quality and high speed data storage and retrieval.
A common class of conventional motor control circuits utilizes a phase-locked-loop (PLL), or frequency-locked-loop (FLL), circuit to drive the stator coils of the polyphase motor. According to this arrangement, a feedback signal from the motor indicates the rotational speed (rpm) of the motor. For example, in a so-called "sensorless" motor, the back emf induced in one of the stator coils that is not being driven in each phase is monitored, and a feedback signal is produced corresponding to the frequency at which the monitored back emf crosses a threshold voltage (i.e., undergoes a "zero crossing"). This feedback signal, corresponding to the speed of the motor, is applied to one input of the PLL or FLL and compared against a reference or command signal to produce a control signal. This control signal is applied to the motor driver circuit to supply current to the stator coils at a magnitude corresponding to the difference between the actual motor speed and the desired speed.
Referring now to FIG. 1, an example of such a conventional PLL/FLL based motor speed control circuit will be described. As shown in FIG. 1, stator coils in motor 10 are driven by output from an operational transconductance amplifier (OTA) 8. A feedback signal indicating the speed at which motor 10 is rotating (e.g., a pulse train having a frequency corresponding to the frequency of back emf zero crossings) is communicated on line FB to one input of phase detector 2; a reference, or command, signal (e.g., a signal having a frequency corresponding to the desired motor speed) is applied to a second input of phase detector 2 on line REF/CMD. Phase detector 2 may have the functionality of conventional phase detector circuitry for motor control, such as that of the MC4044 phase/frequency detector manufactured and sold by Motorola. Phase detector 2 provides output signals on lines LD, LG that consist of pulses indicating whether the feedback signal leads or lags the reference or command signal, respectively, with the duration of each pulse proportional to the phase difference between the two.
In this example, two outputs of phase detector 2 are applied to corresponding inputs of charge pump 4. Charge pump 4 is constructed according to the conventional manner for motor control charge pumps, and as such includes two current sources 6u, 6d connected between a power supply voltage and ground, and controlled by lines LD, LG, respectively. Current sources 6u, 6d, respectively source current to and sink current from the output of charge pump 4 according to the duration of pulses on lines LD, LG, respectively. For example, line LD controls current source 4u to apply a fixed current for a duration corresponding to the time by which the command signal on line REF/CMD leads the feedback signal on line FB in phase or frequency (depending on whether the circuit is implemented as a PLL or an FLL); conversely, line LG controls current source 4d to discharge a fixed current for a duration corresponding to the time by which the command signal on line REF/CMD leads the feedback signal on line FB in phase or frequency. As such, charge pump 4 presents a current-based signal at its output that corresponds to the frequency and duration of the pulses received from phase detector 2.
The output of charge pump 4 is usually applied to an integrating filter 5 to generate a signal on node OUT corresponding to the integral of the current output from charge pump 4, and thus corresponding to a charge having an amount corresponding to the phase or frequency relationship of the command and feedback signals. Node OUT is connected to the input of motor driver 8, which drives stator coils of motor 10 responsive to the signal applied to node OUT. For example, as described in U.S. Pat. No. 5,306,988, issued Apr. 26, 1994, assigned to SGS-Thomson Microelectronics, Inc. and incorporated herein by this reference, the output of motor driver 8 may be applied to the gates of pull-down devices in a push-pull driver circuit during the appropriate phases of the commutation sequence. In this example, if motor 10 is operating slower than desired, for example during motor start up, phase detector 2 will cause a signal to be applied to motor driver 8 to increase the drive current through stator coils in motor 10, thus increasing the motor speed. The construction and operation of motor driver 8 is known in the art, and may include various buffer stages as well as power devices controlled according to the desired commutation sequence and mode.
However, during startup conditions, phase detector 2 will detect that motor 10 is turning at a much slower rate than that indicated by the command signal on line REF/CMD. As such, charge pump 4 will apply its maximum output to the input of motor driver 8 to drive stator coils of motor 10 with the available maximum power. However, this situation can cause overloading of the power supply. Such overloading is especially undesirable in portable personal computers and the like that are powered from batteries.
By way of further background, certain motor control circuits utilize a high level of intelligence, for example implemented into a digital signal processor (DSP), to control the speed of the motor and also limit its current. The use of such high performance processing for motor control results in significantly higher cost, as compared to motor speed control circuits using PLL or FLL control loops.
It is therefore an object of the present invention to provide a motor control circuit that provides speed control while limiting coil current, in a PLL/FLL based motor control circuit.
It is a further object of the present invention to provide such a circuit that does not require series switching to accomplish the current control.
It is a further object to provide an amplifier circuit that can force an output node to a desired level in one mode, and that can be used in a second mode to clamp the signal applied to the output node by another circuit.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.